The present invention relates to the field of integrated circuits and more particularly to integrated circuits having a conductive ground plane overlaying active fine-dimension circuit elements.
Integrated circuits have found wide application in contemporary devices requiring electrical circuitry for sensing information storage and retrieval, control, tabulation, operation, monitoring safety improvement information and status display and a variety of other purposes connected with the devices. In fact, many aspects of contemporary devices which previous to the development of such integrated circuits would have been implemented with analog circuitry and also possibly with the use of hard-wired connections, are now easily implemented in very small size and at lightweight and low power consumption with the use of contemporary integrated circuits. The function and features of those integrated circuits makes available in contemporary devices would be very difficult or impossible to implement using the old hard wired circuit construction commonly used in past years. Such old style construction techniques would effectively prohibit the making of many contemporary devices because of cost, size, weight and power consumption consideration.
Further, many of these contemporary integrated circuits are application-specific integrated circuits (ASIC) type, and are designed and manufactured for a specific application or range of related applications. Because of their specialization to prevent a specific task or range of tasks these ASIC-type integrated circuits bring even greater advantages in reduction in size, weight, and power consumption; while improving function, features, and ease of use in comparison to the general-purpose integrated circuits now available. In complex circuits, with many interconnected transistors, a ground plane can eliminate resonances causing signal attenuation or non-linearity which are critical for analog applications and in more general terms, reduce electrical noise. This type of extraneous signal propagation occurs via the substrate.
The second path for extraneous signal propagation occurs between the integrated lines. The use of the ground plane in silicon allows reduction in cross talk or noise generation on adjacent interconnect lines. The electric field radiating from signal lines terminates on the ground plane rather than coupling to an adjacent line. With a complete ground plane, interlock lines with controlled interphases can also be achieved. This becomes increasingly important at the frequencies at which signals propagate increase leading to enhanced sensitivity of the interconnect line to surroundings. Additionally, for good ESD protection it is required to have a wide ground bus around the edge of the chip is required to the ground plane adjacent to all of the external pins. The wide ground bus reduces the on chip voltage between the entrance and exit points of the ESD currents.
The present invention provides four additional corner pads which are wire bonded to the leadframe. This shunts much of the ESD induced current off the chip and on to the much lower resistance leadframe.